In the past, high speed video cameras that can capture images at high speeds have beer known. For example, a video camera has accomplished high speed image capturing by converting an image size per one image to be processed at a high speed rate into ¼ of the standard image size and placing these four images in an image of the regular rate (see Patent Document “Japanese Patent. Application Laid-Open Publication No. HEI 8-88833”). Another video camera has accomplished high speed image capturing using a circuit structure that processes data received from a sensor in parallel so as to increase a process amount per unit time (see Patent Document “Japanese Patent Application Laid-Open Publication No. HEI 8-251492”).
However, the high speed image capturing described in Patent Document “Japanese Patent Application Laid-Open Publication No. HEI 8-88833” or Patent Document “Japanese Patent Application Laid-Open Publication No. HEI 8-251492” was aimed to temporarily store a captured image in a storage device such as a VTR or a semiconductor memory, reproduce the captured image in slow motion, and analyze a very high speed motion and the device itself had a complicated structure and was expensive. Thus, it was difficult to apply high speed image capturing systems as described in Patent Document 1 or Patent Document 2 to portable image capturing devices that have been widespread as home-use devices, so-called camcorders (product names of devices in which a video camera and a recorder are integrated in one unit), digital cameras, and so forth from view points of portability and power consumption.
With reference to FIG. 1, an image capturing apparatus designed taking account of such points will be described. The structure shown in FIG. 1 has the same structure as that of an existing camcorder. In other words, an image capturing apparatus 100 shown in FIG. 1 includes an image sensor 101, a pre-processing circuit 102, a camera signal processing circuit 103, a conversion processing section 104, a compression and decompression circuit 105, a memory control circuit 106, a memory 107, a display processing circuit 108, a compression and decompression circuit 109, a recording device control circuit 110, a recording device 111, a display section 112, and a control section 113.
The image sensor 101 can select a high speed image capturing mode in which the image sensor 101 reads a signal at a first screen rate (also referred to as frame rate) of 60 fps (fields/second) or more based on the NTSC specifications or a regular image capturing mode in which the image sensor 101 reads a signal at a regular second screen rate. The screen rate in the high speed image capturing mode is 240 fps that is four times higher than that of the regular rate. The image sensor 101 is equipped with a CDS (Correlated Double Sampling) and an A/D converter and the image sensor 101 outputs captured image data.
The pre-processing circuit 102 performs an optically correcting process such as a shading correction for captured image data that are output from the image sensor 101 and outputs a digital image signal. The camera signal processing circuit 103 performs a camera signal process such as a white balance adjustment process for the captured image data that are received from the pre-processing circuit 102.
The conversion processing section 104 performs a display decimation and a size adjustment to convert an image signal received from the camera signal processing circuit 103 into an image signal having a screen rate and a screen size suitable for a display of the display section 112. The display decimation is performed only when an image signal received from the camera signal processing circuit 103 is output to the display processing circuit 108. The display decimation decimates the number of fields per unit time of the image signal captured by the image capturing apparatus 100 in the high speed image capturing mode to the number of fields per unit time defined in the display standard of the display device (60 fps in this case).
The compression and decompression circuit 105 performs a compression-encoding process for captured image data received from the conversion processing section 104 according to a still image encoding system, for example, JPEG (Joint Photographic Experts Group) or the like. In addition, the compression and decompression circuit 105 performs a decompression-decoding process for encoded data of a still image supplied from the memory control circuit 106. The memory control circuit 106 controls writing and reading image data to and from the memory 107. The memory 107 is a FIFO (First In First Out) type buffer memory that temporarily stores image data received from the memory control circuit 106 and, for example, an SDRAM (Synchronous Dynamic Random Access Memory) or the like is used for the memory 107.
The display processing circuit 108 generates an image signal to be displayed on the display section 112 from an image signal received from the conversion processing section 104 or the compression and decompression circuit 109, supplies the signal to the display section 112, and causes it to display an image. The display section 112 is composed, for example, of an LCD (Liquid Crystal Display) and displays a camera-through image that is being captured or a reproduced image of data that have been recorded in the recording device 111.
The compression and decompression circuit 109 performs a compression-encoding process according to a moving image encoding system, for example, MPEG (Moving Picture Experts Group) or the like for image data received from the conversion processing section 104. In addition, the compression and decompression circuit 109 performs a decompression-decoding process for encoded data of a moving image supplied from the recording device 111 and outputs the resultant data to the display processing circuit 108. The display section 112 displays a moving image received from the display processing circuit 108.
The control section 113 is a microcomputer composed, for example, of a CPU (Central Processing Unit), a ROM (Read Only Memory), a RAM (Random Access Memory), and so forth and totally controls each section of the image capturing apparatus by executing programs stored in the ROM and so forth.
In the image capturing apparatus shown in FIG. 1, in the high speed image capturing mode, a captured image signal of 240 fps received from the image sensor 101 is supplied to the camera signal processing circuit 103 through the pre-processing circuit 102. The conversion processing section 104 decimates an output image signal of the camera signal processing circuit 103 by ¼ so that an output signal of 60 fps is obtained. The decimated and size-converted image signal is supplied to the display processing circuit 108. The display processing circuit 108 generates an image signal to be displayed on the display section 112, supplies the resultant image signal to the display section 112, and causes it to display an image.
When receiving a record request of a high speed captured image from the control section 113 according to the user's operation, the conversion processing section 104 sends an image signal of 240 fps to the compression and decompression circuit 105. If necessary, the conversion processing section 104 reduces the size of the image signal received from the camera signal processing circuit 103 and sends the image signal to the compression and decompression circuit 105.
The compression and decompression circuit 105 compression-encodes the image signal received from the conversion processing section 104 according to the JPEG format. The memory control circuit 106 temporarily stores encoded data received from the compression and decompression circuit 105 into the memory 107. In such a manner, image data for a predetermined period are stored in the memory 107.
When receiving a read request for encoded data stored in the memory 107 from the control section 113, the memory control circuit 106 reads the encoded data stored in the memory 107 at 60 fps and sends the encoded data to the compression and decompression circuit 105. The compression and decompression circuit 105 decompression-decodes the encoded data received from the memory control circuit 106 and sends the decoded data to the conversion processing section 104. When receiving a record request for the recording device 111 from the control section 113, the conversion processing section 104 sends the image signal received from the compression and decompression circuit 105 to the compression and decompression circuit 109. The compression and decompression circuit 109 compresses the image signal received from the conversion processing section 104 according to the MPEG format and stores the compression-encoded signal to the recording device 111 through the recording device control circuit 110. The conversion processing section 104 adjusts the size of the image signal of 60 fps received from the compression and decompression circuit 105, sends the resultant image signal to the display processing circuit 108, and causes display section 112 to display a reproduced image.
In the foregoing proposed image capturing apparatus shown in FIG. 1, in the high speed image capturing mode of the image sensor 101, since the screen rate of the output captured signal is high, the pre-processing circuit 102 and the camera signal processing circuit 103 are required to operate at a high speed. If the system is accomplished by an LSI or the like, since the calculation scales of the pre-processing circuit 102 and the camera signal processing circuit 103 are large in the whole system, a high speed process or a parallel process is not advantageous from the view point of circuit area and power consumption. Moreover, in the structure shown in FIG. 1, since a captured image signal was temporarily stored in the memory 107, there was a problem that after the high speed image capturing mode was stopped, it took a process time to decode data temporarily stored in the memory 107 and to re-encode the data according to the regular record format.